Run-Time Scheduling Support for Hybrid CPU/FPGA SoCs

Minimization of system overhead and jitter is a fundamental challenge in the design and implementation of a Real-Time Operating System (RTOS). Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for embedded systems and offer new opportunities to meet these fundamental RTOS challenges. In particular, it is possible to use the hardware resources of an FPGA to handle scheduling of threads. This paper presents the design of such a scheduler for a multithreaded RTOS kernel built on a hybrid FPGA/CPU system. The scheduler module currently provides FIFO, round-robin, and preemptive-priority scheduling services that coordinate both software-resident threads (SW threads) and threads implemented in programmable logic (HW threads). The design has been implemented and experiments show that the hardware-based scheduler module is able to significantly reduce system overhead and jitter due to the ability of the scheduler to field scheduling requests in parallel with application execution. The scheduler module provides constant time scheduling services for up to 256 active threads with a total of 128 different priority levels, while using uniform APIs for threads requesting OS services from either side of the hardware/software boundary.